index - Equipe Secure and Safe Hardware

 

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Linearity Side-channel attack Sensors Reverse engineering SCA Image processing Elliptic curve cryptography FPGA DRAM Robustness Fault injection Magnetic tunnel junction Aging Circuit faults Internet of Things Estimation STT-MRAM Switches RSA Costs Differential power analysis DPA Side-channel analysis Hardware security Side-Channel Attacks Routing OCaml FDSOI Spin transfer torque Reverse-engineering Field programmable gate arrays AES PUF Hardware Dual-rail with Precharge Logic DPL EMFI Computational modeling SoC Memory Controller Machine learning Authentication Defect modeling Transistors Temperature sensors Countermeasures Side-Channel Analysis SCA Resistance Reliability ASIC Confusion coefficient Cryptography Logic gates Voltage Security and privacy CRT Intrusion detection Training Writing Information leakage Fault injection attack CPA TRNG Process variation Electromagnetic Lightweight cryptography Loop PUF Masking countermeasure Field Programmable Gates Array FPGA Randomness Neural networks Formal methods Receivers Simulation Convolution GSM Coq Formal proof 3G mobile communication Countermeasure Energy consumption Asynchronous Dynamic range Masking Application-specific VLSI designs Differential Power Analysis DPA Power-constant logic Power demand Side-channel attacks Fault attacks Side-channel attacks SCA MRAM Gem5 Security services Signal processing algorithms Magnetic tunneling Mutual Information Analysis MIA Random access memory Protocols Side-Channel Analysis Security Filtering

 

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